Nowadays, many electronic devices incorporate functionality that operates at radio frequencies, such as mobile communication devices. The implementation of such functionality in a cost-effective manner is far from trivial. It is well-known that bipolar transistors are particularly suitable for handling signals in the radio frequency (RF) domain. However, the manufacture of integrated circuits (ICs) based on silicon bipolar transistor technology is more complex than for instance complementary metal oxide semiconductor (CMOS) ICs, and the downscaling of the device feature size is more easily achieved in CMOS technology. CMOS devices are able to achieve good RF performances but to reach performances equivalent to bipolar device, the dimensions and thus the technology node of a CMOS device has to be lower than the dimensions and thus the technology node of a bipolar device.
For a given set of specifications including the frequency range, choice has to be made between bipolar at a given node or CMOS at a lower node. Since for small volumes of production such as analog mixed signal (AMS) devices the cost of the masks is an important part of the budget and since this cost increases strongly when going to a lower node, the choice is often made in favor of bipolar and not of CMOS, or in favor of BICMOS that combines bipolar and CMOS devices in a same process flow.
For these reasons, efforts have been made to produce bipolar transistors using a CMOS process flow, thereby providing mixed technology ICs in which bipolar transistors can be used for handling RF signals. An example of such an IC is provided in WO2010/066630 A1.
The challenge that process developers face is that the number of alterations to the CMOS process should remain small whilst at the same time yielding good quality bipolar transistors that are capable of handling high frequency signals. An example of a low-complexity IC including a heterojunction bipolar transistor formed in a CMOS process flow can for instance be found in WO 2003/100845 A1.
It however remains a challenge to improve the design of bipolar transistors, and in particular bipolar transistors manufactured in CMOS manufacturing processes such that the noise of the bipolar transistor decreases and the maximum operating frequency increases, as will be explained in more detail with the aid of FIG. 1 and FIG. 2, which shows a detail of FIG. 1.
The bipolar transistor shown in FIG. 1 comprises a silicon substrate 10 including an active region 11 in which the collector of the bipolar transistor is formed, e.g. by provision of a buried layer in the substrate 10 or by implantation of an impurity into the substrate 10. The active region 11 is defined in between isolation regions 12, e.g. shallow trench isolation (STI) regions. The bipolar transistor further comprises a layer stack including an epitaxially grown base layer, which grows as a monocrystalline region 14 over the silicon substrate 10 and as a polycrystalline region 14′ over the isolation regions 12. A nitride layer (not shown) may be present on the isolation regions 12. A polysilicon base contact layer 16 is present on the base layer, which is covered by an electrically insulating layer 18. An emitter window is defined over the active region 11, in which an emitter material 24 is formed, e.g. As-doped polysilicon, which is electrically insulated from the base contact layer 16 by sidewall spacers 22 in the emitter window and by the electrically insulating layer 18 for the emitter material 24 deposited outside the emitter window 28. The emitter material 24 is electrically insulated from parts of the base region 14 by the remaining portions of an etch stop layer 20, which is used to protect the underlying base layer 14 during the etching of the emitter window in the polysilicon base contact layer 16.
It has been found that a large contribution to the noise figure of the bipolar transistor of FIG. 1 originates from the extrinsic base resistance. Some relevant parts of the base resistance of the bipolar transistor of FIG. 1 are schematically depicted in FIG. 2, which shows an amplified cross-section of the bipolar transistor of FIG. 1. The main extrinsic base resistance is formed by the following components:                the internal resistance of the SiGe in the active device (Rbi_int);        the link resistance corresponding to the space below the spacers (Rlink);        the link resistance corresponding to the space below the etch protect layer (Rxbm);        the resistance of the unsilicided base poly below the emitter-poly extention (Rxbu); and        other resistances such as the resistance between the base contact layer 16 and silicide 28 and between the silicide 28 and the base contact 30.        
From these resistances, the link resistance Rxbm forms the largest contribution to the overall base resistance as in this space, the charge carriers are forced to flow in a narrow as well as long corridor corresponding to the underlying epitaxial base layer 14, which leads to a large resistance.